Book and thesis
Books
New Inter University Electric Circuits II (Co-authored) 2010
Papers
High-Bit-Rate Low-Power Decision Circuit Using InP-InGaAs HBT Technology IEEE J. Solid-State Circuits Vol.40 (No.7) 2005
Papers
High-Bit-Rate Low-Power Decision Circuit Using InP-InGaAs HBT Technology IEEE J. Solid-State Circuits Vol.40 (No.7) 2005
Papers
Recent progress in 40- to 100-Gbit/s-class optical communication ICs using InP-based HBT technologies International Journal of High Speed Electronics and Systems Vol.15 (No.3) 2005
Papers
Recent progress in 40- to 100-Gbit/s-class optical communication ICs using InP-based HBT technologies International Journal of High Speed Electronics and Systems Vol.15 (No.3) 2005
Papers
90 Gbit/s 0.5 W decision circuit using InP/InGaAs double heterojunction bipolar transistors IEE Electron. Lett. Vol.40 (No.16) 2004
Papers
90 Gbit/s 0.5 W decision circuit using InP/InGaAs double heterojunction bipolar transistors IEE Electron. Lett. Vol.40 (No.16) 2004
Papers
3.21 ps ECL gate using InP/InGaAs DHBT technology IEE Electron. Lett. Vol.39 (No.20) 2003
Papers
3.21 ps ECL gate using InP/InGaAs DHBT technology IEE Electron. Lett. Vol.39 (No.20) 2003
Papers
4-bit Multiplexer/Demultiplexer Chip Set for 40-Gbit/s Optical Communication Systems IEEE Transactions on Microwave Theory and Techniques Vol.51 (No.11) 2003
Papers
4-bit Multiplexer/Demultiplexer Chip Set for 40-Gbit/s Optical Communication Systems IEEE Transactions on Microwave Theory and Techniques Vol.51 (No.11) 2003
Papers
Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT IEE Electron. Lett. Vol.39 (No.12) 2003
Papers
Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT IEE Electron. Lett. Vol.39 (No.12) 2003
Papers
A Jitter Suppression Technique for a 2.48832-Gb/s Clock and Data Recovery Circuit IEEE Transactions on Circuits and Systems II. Vol.49 (No.4) 2002
Papers
A Jitter Suppression Technique for a 2.48832-Gb/s Clock and Data Recovery Circuit IEEE Transactions on Circuits and Systems II. Vol.49 (No.4) 2002
Papers
High-Input-Sensitivity, Low-Power 43 Gbit/s Decision Circuit using InP/InGaAs Double-heterojunction Bipolar Transistors IEE Electron, Lett. Vol.38 (No.12) 2002
Papers
High-Input-Sensitivity, Low-Power 43 Gbit/s Decision Circuit using InP/InGaAs Double-heterojunction Bipolar Transistors IEE Electron, Lett. Vol.38 (No.12) 2002
Papers
Low-power 1:16 DEMUX and One-Chip CDR With 1:4 DEMUX Using InP-InGaAs Heterojunction Bipolar Transistors IEEE J. Solid-State Circuits Vol.37 (No.9) 2002
Papers
Low-power 1:16 DEMUX and One-Chip CDR With 1:4 DEMUX Using InP-InGaAs Heterojunction Bipolar Transistors IEEE J. Solid-State Circuits Vol.37 (No.9) 2002
Papers
Very-High-Speed Selector IC using InP/InGaAs Heterojunction Bipolar Transistors IEE Electron. Lett. Vol.38 (No.10) 2002
Papers
Very-High-Speed Selector IC using InP/InGaAs Heterojunction Bipolar Transistors IEE Electron. Lett. Vol.38 (No.10) 2002
Papers
A Jitter Suppression Technique for a Clock Multiplier IEICE Trans. Electron. vol. E-83-C (No.4) 2000
Papers
A Jitter Suppression Technique for a Clock Multiplier IEICE Trans. Electron. vol. E-83-C (No.4) 2000
Papers
Very-High-Speed Si Bipolar Static Frequency Dividers with New T-Type Flip-Flops IEEE J. Solid-State Circuits Vol.30 (No.1) 1995
Papers
Very-High-Speed Si Bipolar Static Frequency Dividers with New T-Type Flip-Flops IEEE J. Solid-State Circuits Vol.30 (No.1) 1995
Papers
High-Bit-Rate, High-Input-Sensitivity Decision Circuit Using Si Bipolar Technology IEEE J. Solid-State Circuits Vol.29 (No.5) 1994
Papers
High-Bit-Rate, High-Input-Sensitivity Decision Circuit Using Si Bipolar Technology IEEE J. Solid-State Circuits Vol.29 (No.5) 1994
Papers
Maximum Operating Frequency in Si Bipolar Master-Slave Toggle Flip-Flop Circuit IEEE J. Solid-State Circuits Vol.29 (No.7) 1994
Papers
Maximum Operating Frequency in Si Bipolar Master-Slave Toggle Flip-Flop Circuit IEEE J. Solid-State Circuits Vol.29 (No.7) 1994
Papers
Sub-100-nm-Scale Patterning Using a Low-Energy Electron Beam Jpn. J. Appl. Phys.L744. 31 1992
Papers
Sub-100-nm-Scale Patterning Using a Low-Energy Electron Beam Jpn. J. Appl. Phys.L744. 31 1992
Papers
Very-Low-Energy Electron Beam Lithography Using a Retarding Field Jpn. J. Appl. Phys. 2212. 29 1990
Papers
Very-Low-Energy Electron Beam Lithography Using a Retarding Field Jpn. J. Appl. Phys. 2212. 29 1990
Papers
The Interfacial Characteristics of MIS Structures Using Carbon Films as Insulator The Transactions of The IECE of JAPAN Vol.E69 (No.4) 1986
Papers
The Interfacial Characteristics of MIS Structures Using Carbon Films as Insulator The Transactions of The IECE of JAPAN Vol. E69 (No.4) 1986